The present invention relates generally to integrated circuits and, more particularly, to a process for forming dual damascene structures in an integrated circuit.
Single damascene is an interconnection fabrication process for integrated circuits in which grooves are formed in an insulating layer and filled with a conductive material to form interconnects. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive contact (or via) openings are also formed in the insulating layer. A conductive material is formed in the grooves and conductive contact (or via) openings.
In one standard dual damascene process, a first oxide layer is deposited over a conductive structure. A hard mask is formed over the first oxide layer and a first patterned photoresist layer is formed on the hard mask. The hard mask is patterned using the first photoresist layer as a pattern. The first photoresist layer is removed and a second oxide layer is then formed over the hard mask.
A second patterned photoresist layer is formed over the second oxide layer. Both the first oxide layer and the second oxide layer are etched to form the dual damascene opening. The first oxide layer is etched using the hard mask as a pattern and the underlying conductive structure as an etch stop. The second oxide layer is etched using the second photoresist layer as a pattern and the hard mask as an etch stop. The second photoresist layer is then stripped.
This process involves a combination of different steps to form the dual damascene structure. For example, the hardmask is patterned prior to forming the second dielectric layer. Thus, the partially fabricated integrated circuit is transferred between different processing systems to perform the different deposition and patterning steps.
In another dual damascene process, a dielectric is formed and patterned using a first photoresist. The first photoresist is removed and the dielectric is patterned again using a second photoresist. The vias and grooves are formed using the different patterning steps. This process uses a timed etch to control the depth of the grooves. This process is difficult to control. Thus, it is desirable to develop a process that reduces the complexity of the process to form a dual damascene structure.
The present invention is directed to a process for forming a dual damascene structure. The process includes forming a stack including insulating layers and a stop layer where two masks are formed above the stack. One of the masks is used to form via or contact openings in the insulating layers and the second mask is used to form grooves for interconnections in the insulating layers. In one embodiment, the via or contact openings are formed prior to the grooves.
By using the two mask layers after the stack is formed, the number of processing steps and movement of the partially fabricated integrated circuit between systems may be reduced. In other words, the insulating layers and the etch stop may be formed and then subsequently patterned to form the dual damascene structure. Further, the insulating layer and the etch stop layer may be formed in the same chamber or cluster of chambers.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.